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[MPI] arban

Description: 这是一个用verilog实现的除法器代码。-This is a realization of the use verilog divider code.
Platform: | Size: 1024 | Author: arban | Hits:

[VHDL-FPGA-Verilog] divide

Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
Platform: | Size: 1024 | Author: lyy | Hits:

[Software Engineering] pld

Description: 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER， 设计一个20bit的up_only COUNTER, 要求该COUNTER在FE0FA和FFFFF之间自动循环计数； 分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、 EPF10K70RC240-4几种芯片中的最大工作频率； 请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来 （仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the MegaWizard Plug-In Manager in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency).
Platform: | Size: 31744 | Author: 李侠 | Hits:

[VHDL-FPGA-Verilog] divide

Description: Verilog hdl语言的常用除法器设计，可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[VHDL-FPGA-Verilog] divide

Description: It is n-bit sequential divider in verilog language
Platform: | Size: 1024 | Author: Lisha | Hits:

[VHDL-FPGA-Verilog] JPEG2000

Description: jpeg 2000 encoder complete document
Platform: | Size: 378880 | Author: ibbu | Hits:

[Other] clk_div

Description: 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.
Platform: | Size: 199680 | Author: 颜爱良 | Hits:

[VHDL-FPGA-Verilog] divide

Description: 关于verilog的分频程序 等占空比 非等占空比 小数分频 奇数分频-Verilog frequency on the sub-procedures such as the duty cycle of non-duty-cycle fractional odd frequency, etc.
Platform: | Size: 3072 | Author: 杜方 | Hits:

[VHDL-FPGA-Verilog] div_n_0_5

Description: 使用verilog实现任意奇数n+0.5分频，使用ise11.1和modelsim se6.5仿真测试-Using an arbitrary odd number n+0.5 verilog divide, the use of simulation testing ise11.1 and modelsim se6.5
Platform: | Size: 788480 | Author: linzi | Hits:

[VHDL-FPGA-Verilog] Test

Description: verilog语言编写的分频程序及其testbench测试文件。fpga开发入门的好例子。-verilog divide written test procedures and testbench files. fpga development of entry-a good example.
Platform: | Size: 1024 | Author: 刘进 | Hits:

[VHDL-FPGA-Verilog] 8fenpin-verilog

Description: 用verilog HDL实现8分频，可作为时钟8分频器-Verilog divide by 8 to achieve
Platform: | Size: 9216 | Author: qhd | Hits:

[VHDL-FPGA-Verilog] divide

Description: divide模块，实现除法功能。该module是用Verilog编写的，压缩包里包括了设计程序以及测试程序（testbench）。-divide module, the division function. The module is written in Verilog, compression bag, including the design process and testing process Sequence (testbench).
Platform: | Size: 31744 | Author: 周狩猎 | Hits:

[VHDL-FPGA-Verilog] verilog--divide-programs

Description: verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process
Platform: | Size: 578560 | Author: ni husheng | Hits:

[Other] Verilog-Reference-routines

Description: verilog 参考例程。适合初学者学习，深入浅出，由简到难，逐步深化，各个击破。 -verilog Reference routines. For beginners learning, easily understood, by Jane to difficult, and gradually deepening, divide and conquer.
Platform: | Size: 2548736 | Author: 叶胜东 | Hits:

[Other] VerilogFreq-div

Description: Verilog分频程序原理讲解及代码.偶数倍分频奇数倍分频的原理和方法-Verilog divide the program explain the principle and code an even multiple of odd multiple of the principle of divide and divide
Platform: | Size: 6144 | Author: wangfan | Hits:

[VHDL-FPGA-Verilog] divide

Description: 用veriog实现的任意位数的除法，在modelism中验证过了已经。-Implementation division with verilog.
Platform: | Size: 1024 | Author: yangyang | Hits:

[Software Engineering] verilog--ok

Description: 二 分 频 二 分 频-Divide divide divide
Platform: | Size: 3466240 | Author: 行 | Hits:

[VHDL-FPGA-Verilog] Verilog-Divide-by-3-Counter

Description: Verilog Divide by 3 Counter
Platform: | Size: 10240 | Author: cmags | Hits:

[VHDL-FPGA-Verilog] Verilog-Divide-by-45-Counter

Description: Verilog Divide by 4.5 Counter
Platform: | Size: 10240 | Author: cmags | Hits:

[VHDL-FPGA-Verilog] divide-freq

Description: 基于XILINX芯片的verilog程序。调用DCM模块，完成50MHz转换75MHz，相位偏移90°-XILINX chip based on Verilog program. Call the DCM module to complete the 50MHz conversion, 75MHz, phase shift of 90 degrees
Platform: | Size: 2827264 | Author: 薛佳 | Hits:
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